The present invention relates to a programmable integrated circuit device, and in particular to a integrated device that facilitates modifying executable program instructions and/or data stored on the integrated circuit device.
Microprocessors, signal processors, and the like have been known for many years in the various designs. These program-controlled units are often designed to execute programs stored in a program memory that is located within the program-controlled unit.
Non-volatile memory devices, such as a ROM, are frequently used as program memory, and may be external to or integral with the program controlled unit. However, a problem with the use of a ROM is that it is difficult to change the contents of the memory device when the executable instructions and/or data stored therein need to be updated. For example, when a new version of software/firmware is released. Replacing the ROM in its entirety with a new ROM that includes the updated firmware is often difficult and expensive.
One technique for updating the firmware is to use a transfer instruction that modifies the old/defective program code (i.e., a patch). This transfer instruction is executed when the program accesses this defective program code at a pre-specified address assigned to this program code. For every defective program code in the ROM, a certain amount of storage space in an internal or external non-volatile memory device (i.e., a RAM) is made available to accommodate the follow-on instruction associated with the transfer instruction (i.e., interrupt service routine). When the system is being initialized, the addresses assigned to the old/defective program codes are programmed in a register assigned to the respective transfer instruction, and the associated transfer follow-on instructions are loaded into the system RAM. Modified or corrected transfer follow-on instructions of this kind are often referred to as error correction instructions or patches and the associated memory is referred to as patch memory. The data for the transfer follow-on instructions can be loaded into the system RAM from a system EEPROM or through an external interface.
Individual erroneous program codes may be corrected in this way, but a considerable amount of storage in the system RAM is necessary for this, and therefore RAM storage space is no longer available for further tasks.
In addition, an erroneous program code cannot be corrected or manipulated directly, but rather only through the detour of a transfer instruction and its associated follow-on instruction. When a single erroneous byte appears in a program table that is used in many program sequences, all these program sequences must be corrected and/or manipulated. Since a separate interrupt is needed for this every time, for which a correspondingly large amount of storage space must be made available on the system RAM, this technique quickly becomes rather complicated.
Another problem with the prior art techniques is that the execution time of each erroneous program code is increased by the time needed for the interrupt. This is especially undesirable in the case of erroneous program codes that are frequently addressed during execution of a program, since this may substantially reduce the performance of the entire system.
Therefore, there is a need for a technique that allows executable program instructions/data to be easily updated within a programmable integrated circuit device.
Briefly, according to an aspect of the present invention, a circuit arrangement for replacement of executable program instructions and data includes a data bus, an address bus, a memory device that is coupled to the address and data buses to store executable program instructions and data, and a programmable patch-memory module also coupled to the address and data buses. The patch memory module includes a patch address data storage device that stores and provides a patch address value indicative of an address within the memory device the contents of which is being updated, and a comparator that is coupled to the address bus and compares an address signal value on the address bus with the patch address value. The comparator provides a comparator status signal indicative of whether or not there is a match. The patch memory module also includes a patch data storage device that stores a patch data value, and outputs the patch data value onto the data bus when the comparator status signal indicates a match.
The present invention facilitates correction of erroneous instructions or program sequences. For example, an address belonging to the datum that needs to be replaced is read in by the memory device via the data/address bus (as usual) and also, at the same time, by the patch-memory module. The patch-memory module compares the addresses forwarded via the data/address bus to the memory with a given address pattern stored in the patch address data storage device within the module. If the address pattern in the patch-memory module agrees with the address on the address bus, the patch memory module outputs a patch data value onto the data bus, rather than allowing the memory device to output data in response to the address on the address bus.
The circuit arrangement preferably is an integrated circuit (i.e., the memory device and the patch-memory module are integrated on one semiconductor chip). The address/data bus is an internal bus. Consequently, the patch-memory module accesses the internal address/data bus quickly and is synchronized with access to the memory.
In one embodiment, through the use of dedicated registers (i.e., the patch-address registers, and the patch-enable register) the RAM essentially can be dispensed with for error correction. Only if correcting large erroneous program sequences, which are larger than the number of implemented patch data memories, does it make sense to branch off into the RAM. This can be implemented, for example, by a transfer instruction that branches off to a new, improved program sequence in the RAM. Thus even complex software or program modules can be inserted or replaced.
An advantage of using patch-data memories and patch-address memories structured as registers is the relatively delay-free access. In known patch-memory modules, the data that needs to be replaced or corrected are typically stored in a RAM or ROM. To replace the erroneous data with the error-free ones from the patch-data memory, access to the patch-data memory is required thus significantly reducing the data read-out speed, especially if the data needing to be replaced occurs very frequently during the program execution. Structuring the patch-data memory and patch-address memory respectively as a hard-wired logic circuit and as registers assures that the data can be read out and replaced almost without delay.
Data can also be replaced. For example, if a single byte needs to be changed in a table that is used simultaneously in several program sequences, this may be performed by simply changing this one byte.